5-Level Paging and 5-Level EPT

This document describes planned extensions to the Intel 64 architecture to expand the
size of addresses that can be translated through a processor’s memory-translation
hardware.
Modern operating systems use address-translation support called paging. Paging
translates linear addresses (also known as virtual addresses), which are used by
software, to physical addresses, which are used to access memory (or memory-
mapped I/O). Section 1.1 describes the 64-bit paging hardware on Intel 64 processors.
Existing processors limit linear addresses to 48 bits. Chapter 2 describes paging
extensions that would relax that limit to 57 linear-address bits.
Virtual-machine monitors (VMMs) use the virtual-machine extensions (VMX) to
support guest software operating in a virtual machine. VMX transitions are control-
flow transfers between the VMM and guest software. VMX transitions involve the
loading and storing of various processor registers. Some of these registers are defined
to contain linear addresses. Because of this, the operation of VMX transitions depends
in part on the linear-address width supported by the processor. Section 1.2 describes
the existing treatment of linear-address registers by VMX transitions, while Chapter 3
describes the changes required to support larger linear addresses.
VMMs may also use additional address-translation support called extended page
tables (EPT). When EPT is used, paging produces guest-physical addresses, which
EPT translates to physical addresses. Section 1.3 describes the EPT hardware on
existing Intel 64 processors, which limit guest-physical addresses to 48 bits. Chapter 4
describes EPT extensions to support 57 guest-physical-address bits